`timescale 1ns / 1ps


module top();

reg sys_clk, sys_rst;
reg bit_in;
wire bit_out1, bit_out2, bit_out3;
reg[31:0] bits = 32'b0101_1011_1011_1101_1111_0111_1110_1111;

DELAY_BITS
    #(
        .n_delay(1)
    )
    bit_d1(
        .clk(sys_clk),
        .rst(sys_rst),
        .bit_in(bit_in),
        .bit_out(bit_out1)
    );

DELAY_BITS
    #(
        .n_delay(2)
    )
    bit_d2(
        .clk(sys_clk),
        .rst(sys_rst),
        .bit_in(bit_in),
        .bit_out(bit_out2)
    );

DELAY_BITS
    #(
        .n_delay(3)
    )
    bit_d3(
        .clk(sys_clk),
        .rst(sys_rst),
        .bit_in(bit_in),
        .bit_out(bit_out3)
    );

initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,top);
end

// sys_clk
initial begin
	// rst = 0;
	sys_clk = 0;
	forever #10 sys_clk = ~sys_clk;
end

reg[7:0] cnt = 8'd0;
always@( posedge sys_clk or posedge sys_rst ) begin
    if( sys_rst ) begin
        cnt     <= 8'd0;
        bit_in  <= 1'b0;
    end
    else begin
        if( cnt <= 8'd31 ) begin
            bit_in  <= bits[31-cnt];
            cnt     <= cnt + 8'd1;
        end
        else
            cnt <= 8'd0;
    end
end

initial begin
    #15    sys_rst = 1'b0;
    #6     sys_rst = 1'b1;
    #60    sys_rst = 1'b0;
    #1000;
	$finish;
end


endmodule
